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ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 1 4252b12f typical application features description negative voltage hot swap controllers the lt c ? 4252 negative voltage hot swap tm controller allows a board to be safely inserted and removed from a live backplane . output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. adjustable undervoltage and overvoltage detectors dis- connect the load whenever the input supply exceeds the desired operating range. the ltc4252s supply input is shunt regulated, allowing safe operation with very high supply voltages. a multifunction timer delays initial start- up and controls the circuit breakers response time. the circuit breakers response time is accelerated by sensing excessive mosfet drain voltage, keeping the mosfet within its safe operating area (soa). an adjustable soft- start circuit controls mosfet inrush current at start-up. the ltc4252-2 provides automatic retry after a fault. the ltc4252 c -1/ltc4252c -2 feature tight 1% undervoltage / overvoltage threshold accuracy. the ltc4252 is available in either an 8-pin or 10-pin msop. the ltc4252b and ltc4252c improve the ruggedness of the shunt regulator in the ltc4252 and ltc4252a. C48v/2.5a hot swap controller start -up behavior applications n allows safe board insertion and removal from a live C 48v backplane n floating topology permits very high voltage operation n current limit with circuit breaker timer n fast response time limits peak fault current n programmable soft-start current limit n programmable timer with drain voltage accelerated response n 1% undervoltage / overvoltage threshold ( ltc4252c ) n improved ruggedness shunt regulator adjustable undervoltage/ overvoltage protection ltc4252b-1/ltc4252c-1: latch off after fault ltc4252b-2/ltc4252c-2: automatic retry after fault available in 8-pin and 10-pin msop packages n hot board insertion n electronic circuit breaker n C 48v distributed power systems n negative power supply control n central office switching n high availability servers n atca l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 4252b12 ta01 ?48rtn ov uv v ee v in sense ss timer gate pwrgd drain ltc4252b-1 r1 402k 1% r2 32.4k 1% c t 0.33f d in ? ddz13b ** c ss 68nf c c 18nf ?48v r s 0.02 q1 irf530s v out r c 10 r3 5.1k r in 3 1.8k in series 1/4w each c1 10nf c in 1f c l 100f ?48rtn (short pin) + r d 1m load en * * m0c207 **diodes, inc ? recommended for harsh environments 4252b12 ta01a gate 5v/div sense 2.5a/div pwrgd 10v/div 1ms/div v out 20v/div
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 2 4252b12f absolute maximum ratings current into v in (100 s pulse ) ............................. 100 ma v in , drain pin minimum voltage ........................ C 0.3 v input / output pins ( except sense and drain ) voltage .......... C0.3 v to 16 v sense pin voltage .................................... C0.6 v to 16 v current out of sense pin (20 s pulse ) .......... C200 ma current into drain pin (100 s pulse ) ................... 20 ma maximum junction temperature .......................... 125 c all voltages referred to v ee (note 1) 1 2 3 4 8 7 6 5 top view ms8 package 8-lead plastic msop v in ss sense v ee timer uv/ov drain gate t jmax = 125c, ja = 160c/w 1 2 3 4 5 v in pwrgd ss sense v ee 10 9 8 7 6 timer uv ov drain gate top view ms package 10-lead plastic msop t jmax = 125c, ja = 160c/w pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc4252bcms8-1#pbf ltc4252bcms8-1#trpbf ltgdx 8-lead plastic msop 0c to 70c ltc4252bcms8-2#pbf ltc4252bcms8-2#trpbf ltgdz 8-lead plastic msop 0c to 70c ltc4252bims8-1#pbf ltc4252bims8-1#trpbf ltgdx 8-lead plastic msop C40c to 85c ltc4252bims8-2#pbf ltc4252bims8-2#trpbf ltgdz 8-lead plastic msop C40c to 85c ltc4252bcms-1#pbf ltc4252bcms-1#trpbf ltgdy 10-lead plastic msop 0c to 70 c ltc4252bcms-2#pbf ltc4252bcms-2#trpbf ltgfb 10-lead plastic msop 0c to 70c ltc4252bims-1#pbf ltc4252bims-1#trpbf ltgdy 10-lead plastic msop C40c to 85c ltc4252bims-2#pbf ltc4252bims-2#trpbf ltgfb 10-lead plastic msop C40c to 85c ltc4252ccms-1#pbf ltc4252ccms-1#trpbf ltgfc 10-lead plastic msop 0c to 70c ltc4252ccms-2#pbf ltc4252ccms-2#trpbf ltgfd 10-lead plastic msop 0c to 70c ltc4252cims-1#pbf ltc4252cims-1#trpbf ltgfc 10-lead plastic msop C40 c to 85c ltc4252cims-2#pbf ltc4252cims-2#trpbf ltgfd 10-lead plastic msop C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating temperature range ltc 4252 bc -1/ ltc 4252 bc -2 ltc 4252 cc -1/ ltc 4252 cc -2 .................... 0 c to 70 c ltc 4252 bi -1/ ltc 4252 bi -2 ltc 4252 ci -1/ ltc 4252 ci -2 ................. C40 c to 85 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 300 c
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 3 4252b12f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 2) symbol parameter conditions ltc4252b-1/-2 ltc4252c-1/-2 units min typ max min typ max v z v in C v ee zener voltage i in = 2ma l 11.5 13 14.5 11.5 13 14.5 v r z v in C v ee zener dynamic impedance i in = 2ma to 30ma 5 5 i in v in supply current uv = ov = 4v, v in = (v z C 0.3v) 0.8 2 0.9 2 ma v lko v in undervoltage lockout coming out of uvlo (rising v in ) 9.2 11.5 9 10 v v lkh v in undervoltage lockout hysteresis 1 0.5 v v cb circuit breaker current limit voltage v cb = (v sense C v ee ) 40 50 60 45 50 55 mv v acl analog current limit voltage v acl = (v sense C v ee ), ss = open or 2.2v 80 100 120 mv v acl / v cb analog current limit voltage/ circuit breaker voltage v acl = (v sense C v ee ), ss = open or 1.4v 1.05 1.20 1.38 v/v v fcl fast current limit voltage v fcl = (v sense C v ee ) 150 200 300 150 200 300 mv v ss ss voltage after end of ss timing cycle 2.2 1.4 v r ss ss output impedance 100 50 k i ss ss pin current uv = ov = 4v, v sense = v ee , v ss = 0v ( sourcing) 22 28 a uv = ov = 0v, v sense = v ee , v ss = 2v (sinking) 28 28 ma v os analog current limit offset voltage 10 10 mv v acl +v os / v ss ratio (v acl + v os ) to ss voltage 0.05 0.05 v/v i gate gate pin output current uv = ov = 4 v, v sense = v ee , v gate = 0v ( sourcing) 40 58 80 40 58 80 a uv = ov = 4v, v sense C v ee = 0.15v, v gate = 3v (sinking) 17 17 ma uv = ov = 4v, v sense C v ee = 0.3v, v gate = 1v (sinking) 190 190 ma v gate external mosfet gate drive v gate C v ee , i in = 2ma 10 12 v z 10 12 v z v v gateh gate high threshold v gateh = v in C v gate , i in = 2ma, for pwrgd status (ms only ) 2.8 2.8 v v gatel gate low threshold (before gate ramp-up) 0.5 0.5 v v uvhi uv pin threshold high 3.075 3.225 3.375 v v uvlo uv pin threshold low 2.775 2.925 3.075 v v uv uv pin threshold low-to-high transition 3.05 3.08 3.11 v v uvhst uv pin hysteresis ( for ltc4252c only) 300 292 324 356 mv v ovhi ov pin threshold high 5.85 6.15 6.45 v v ovlo ov pin threshold low 5.25 5.55 5.85 v v ov ov pin threshold low-to-high transition 5.04 5.09 5.14 v v ovhst ov pin hysteresis ( for ltc4252c only) 600 82 102 122 mv i sense sense pin input current uv = ov = 4v, v sense = 50mv C 15 C30 C15 C30 a i inp uv, ov pin input current uv = ov = 4v 0.1 1 0.1 1 a v tmrh timer pin voltage high threshold 4 4 v v tmrl timer pin voltage low threshold 1 1 v
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 4 4252b12f symbol parameter conditions ltc4252b-1/-2 ltc4252c-1/-2 units min typ max min typ max i tmr timer pin current timer on (initial cycle/latchoff/ shutdown cooling, sourcing), v tmr = 2v 5.8 5.8 a timer off (initial cycle, sinking), v tmr = 2v 28 28 ma timer on ( circuit breaker, sourcing, i drn = 0a), v tmr = 2v 230 230 a timer on ( circuit breaker, sourcing, i drn = 50a), v tmr = 2v 630 630 a timer off ( circuit breaker/ shutdown cooling, sinking), v tmr = 2v 5.8 5.8 a ?i tmracc / ?i drn [(i tmr at i drn = 50a) C (i tmr at i drn = 0a)]/?i drn timer on ( circuit breaker with i drn = 50a) 8 8 a/a v drnl drain pin voltage low threshold for pwrgd status (ms only) 2.385 2.385 v i drnl drain leakage current v drain = 5v (4v for ltc4252c) 0.1 1 0.1 1 a v drncl drain pin clamp voltage i drn = 50a 7 6 v v pgl pwrgd output low voltage i pg = 1.6ma (ms only) i pg = 5ma (ms only) 0.2 0.4 1.1 0.2 0.4 1.1 v v i pgh pwrgd pull-up current v pwrgd = 0v ( sourcing) (ms only) 40 58 80 40 58 80 a t ss ss default ramp period ss pin floating, v ss ramps from 0.2v to 2v 180 s ss pin floating, v ss ramps from 0.1v to 0.9v 230 s t pllug uv low to gate low 0.4 0.4 s t phlog ov high to gate low 0.4 0.4 s electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee unless otherwise specified.
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 5 4252b12f typical performance characteristics i in vs v in undervoltage lockout v lko vs temperature undervoltage lockout hysteresis v lkh vs temperature circuit breaker current limit voltage v cb vs temperature analog current limit voltage v acl vs temperature fast current limit voltage v fcl vs temperature v z vs temperature r z vs temperature i in vs temperature temperature (c) ?55 v z (v) 14.5 14.0 13.5 13.0 12.5 12.0 ?15 25 45 125 4252b12 g01 ?35 5 65 85 105 i in = 2ma temperature (c) ?55 r z () 10 9 8 7 6 5 4 3 2 ?15 25 45 125 4252b12 g02 ?35 5 65 85 105 i in = 2ma temperature (c) ?55 i in (a) 2000 1800 1600 1400 1200 1000 800 600 400 200 0 ?15 25 45 125 4252b12 g03 ?35 5 65 85 105 v in = (v z ? 0.3v) v in (v) 0 2 4 6 8 10 12 14 16 18 20 22 i in (ma) 1000 100 10 1 0.1 4252b12 g04 125c 85c 25c ?40c temperature (c) ?55 v lko (v) 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 ?15 25 45 125 4252b12 g05 ?35 5 65 85 105 temperature (c) ?55 0.5 v lkh (v) 0.7 1.1 1.3 1.5 ?15 25 45 125 4252b12 g06 0.9 ?35 5 65 95 105 temperature (c) ?55 v cb (mv) 60 58 56 54 52 50 48 46 44 42 40 ?15 25 45 125 4252b12 g07 ?35 5 65 85 105 temperature (c) ?55 v acl (mv) 120 115 110 105 100 95 90 85 80 ?15 25 45 125 4252b12 g08 ?35 5 65 85 105 temperature (c) ?55 v fcl (mv) 300 275 250 225 200 175 150 ?15 25 45 125 4252b12 g09 ?35 5 65 85 105
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 6 4252b12f typical performance characteristics v os vs temperature (v acl + v os )/v ss vs temperature i gate (sourcing) vs temperature i gate (acl, sinking) vs temperature i gate (fcl, sinking) vs temperature v gate vs temperature v ss vs temperature r ss vs temperature i ss (sinking) vs temperature temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 v ss (v) 4252b12 g10 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 r ss (k) 4252b12 g11 110 108 106 104 102 100 98 96 94 92 90 temperature (c) ?55 ?35 ?15 0 i ss (ma) 5 15 20 25 65 85 105 45 4252b12 g12 10 5 25 45 125 30 35 40 uv = ov = v sense = v ee i in = 2ma v ss = 2v temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 v os (mv) 4252b12 g13 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 9.0 temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 (v acl + v os ) / v ss (v/v) 4252b12 g14 0.060 0.058 0.056 0.054 0.052 0.050 0.048 0.046 0.044 0.042 0.040 temperature (c) ?55 i gate (a) 70 65 60 55 50 45 40 ?15 25 45 125 4252b12 g15 ?35 5 65 85 105 uv/0v = 4v timer = 0v v sense = v ee v gate = 0v temperature (c) ?55 i gate (ma) 30 25 20 15 10 5 0 ?15 25 45 125 4252b12 g16 ?35 5 65 85 105 uv/0v = 4v timer = 0v v sense ? v ee = 0.15v v gate = 3v temperature (c) ?55 i gate (ma) 400 350 300 250 200 150 100 50 0 ?15 25 45 125 4252b12 g17 ?35 5 65 85 105 uv/0v = 4v timer = 0v v sense ? v ee = 0.3v v gate = 1v temperature (c) ?55 v gate (v) 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 ?15 25 45 125 4252b12 g18 ?35 5 65 85 105 uv/0v = 4v timer = 0v v sense = v ee
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 7 4252b12f typical performance characteristics ov threshold vs temperature i sense vs temperature i sense vs (v sense C v ee ) timer threshold vs temperature i tmr (initial cycle, sourcing) vs temperature i tmr (initial cycle, sinking) vs temperature v gateh vs temperature v gatel vs temperature uv threshold vs temperature temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 v gateh (v) 4252b12 g19 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 v gateh = v in ? v gate , i in = 2ma (ms only) temperature (c) ?55 v gatel (v) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?15 25 45 125 4252b12 g20 ?35 5 65 85 105 uv/0v = 4v timer = 0v gate threshold before ramp-up temperature (c) ?55 uv threshold (v) 3.375 3.275 3.175 3.075 2.975 2.875 2.775 ?15 25 45 125 4252b12 g21 ?35 5 65 85 105 v uvh v uv v uvl temperature (c) ?55 ov threshold (v) 6.45 6.25 6.05 5.85 5.65 5.45 5.25 5.05 4.85 ?15 25 45 125 4252b12 g22 ?35 5 65 85 105 v ovh v ovl v ov temperature (c) ?55 i sense (a) ?10 ?12 ?14 ?16 ?18 ?20 ?22 ?24 ?26 ?28 ?30 ?15 25 45 125 4252b12 g23 ?35 5 65 85 105 uv/0v = 4v timer = 0v gate = high v sense ? v ee = 50mv (v sense ? v ee ) (v) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?i sense (ma) 0.01 0.1 1.0 10 100 1000 4252b12 g24 uv/0v = 4v timer = 0v gate = high t a = 25c temperature (c) ?55 timer threshold (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?15 25 45 125 4252b12 g25 ?35 5 65 85 105 v tmrh v tmrl temperature (c) ?55 i tmr (a) 10 9 8 7 6 5 4 3 2 1 0 ?15 25 45 125 4252b12 g26 ?35 5 65 85 105 timer = 2v temperature (c) ?55 i tmr (ma) 50 45 40 35 30 25 20 15 10 ?15 25 45 125 4252b12 g27 ?35 5 65 85 105 timer = 2v
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 8 4252b12f typical performance characteristics i tmr vs i drn ?i tmracc /?i drn vs temperature i drn vs v drain v drnl vs temperature v drncl vs temperature v pgl vs temperature i tmr (circuit breaker, sourcing) vs temperature i tmr ( circuit breaker, i drn = 50a , sourcing) vs temperature i tmr (cooling cycle, sinking) vs temperature temperature (c) ?55 i tmr (a) 280 260 240 220 200 180 ?15 25 45 125 4252b12 g28 ?35 5 65 85 105 timer = 2v i drn = 0a temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 550 i tmr (a) 570 590 610 690 4252b12 g29 630 650 670 timer = 2v i drn = 50a temperature (c) ?55 i tmr (a) 10 9 8 7 6 5 4 3 2 1 0 ?15 25 45 125 4252b12 g30 ?35 5 65 85 105 timer = 2v i drn (ma) 0.001 0.01 0.1 i tmr (ma) 1 10 0.1 1 10 4252b12 g31 temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 ?i tmracc /i drn (a/a) 4252b12 g32 9.0 8.8 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 timer on (circuit breaking, i drn = 50a) v drain (v) 0 2 4 6 8 10 12 14 16 i drn (ma) 100 10 1 0.1 0.01 0.001 0.0001 0.00001 4252b12 g33 i in = 2ma 125c 85c 25c ?40c temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 v drnl (v) 4252b12 g34 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 for pwrgd status (ms only) temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 v drncl (v) 4252b12 g35 8.0 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 i drn = 50a temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 v pgl (v) 4252b12 g36 3.0 2.5 2.0 1.5 1.0 0.5 0 (ms only) i pg = 10ma i pg = 5ma i pg = 1.6ma
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 9 4252b12f pin functions v in (pin 1/pin 1): positive supply input. connect this pin to the positive side of the supply through a dropping resistor. a shunt regulator clamps v in at 13v. an internal undervoltage lockout (uvlo) circuit holds gate low until the v in pin is greater than v lko , overriding uv and ov. if uv is high, ov is low and v in comes out of uvlo, timer starts an initial timing cycle before initiating a gate ramp- up. if v in drops below approximately 8.2v, gate pulls low immediately. pwrgd (pin 2/not available ): power good status output (ms only). at start-up, pwrgd latches low if drain is below 2.385v and gate is within 2.8v of v in . pwrgd status is reset by uv, v in (uvlo) or a circuit breaker fault timeout. this pin is internally pulled high by a 58a current source. ss (pin 3/pin 2): soft-start pin. this pin is used to ramp inrush current during start up, thereby effecting control over di/dt. a 20x attenuated version of the ss pin voltage is presented to the current limit amplifier. this attenuated voltage limits the mosfet s drain current through the sense resistor during the soft-start current limiting. at the begin- ning of a start-up cycle, the ss capacitor (c ss ) is ramped by a 22a (28a for the ltc4252c) current source . the gate pin is held low until ss exceeds 20 ? v os = 0.2v. ss is internally shunted by a 100k resistor (r ss ) which limits the ss pin voltage to 2.2v (50k resistor and 1.4v for the ltc4252c). this corresponds to an analog current limit sense voltage of 100mv (60mv for the ltc4252c ). if the ss capacitor is omitted, the ss pin ramps up in about 180s. the ss pin is pulled low under any of the following conditions: in uvlo, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. sense (pin 4/pin 3): circuit breaker/current limit sense pin. load current is monitored by a sense resistor r s con- nected between sense and v ee , and controlled in three steps. if sense exceeds v cb (50mv), the circuit breaker comparator activates a (230a + 8 ? i drn ) timer pull-up current. if sense exceeds v acl , the analog current limit amplifier pulls gate down to regulate the mosfet current at v acl /r s . in the event of a catastrophic short- circuit, sense may overshoot. if sense reaches v fcl (200mv), the fast current limit comparator pulls gate low with a strong pull-down. to disable the circuit breaker and cur - rent limit functions, connect sense to v ee . (ms/ms8) typical performance characteristics i pgh vs temperature t ss vs temperature t pllug and t phlog vs temperature temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 i pgh (a) 4252b12 g37 62 61 60 59 58 57 56 55 v pwrgd = 0v (ms only) temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 t ss (s) 4252b12 g38 220 210 200 190 180 170 160 150 ss pin floating, v ss ramps from 0.2v to 2v temperature (c) ?55 delay (s) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?15 25 45 125 4252b12 g39 ?35 5 65 85 105 t pllug t phlog
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 10 4252b12f pin functions (ms/ms8) v ee (pin 5/pin 4): negative supply voltage input. connect this pin to the negative side of the power supply. gate ( pin 6/ pin 5): n - channel mosfet gate drive output . this pin is pulled high by a 58a current source . gate is pulled low by invalid conditions at v in (uvlo), uv, ov, or a circuit breaker fault timeout. gate is actively servoed to control the fault current as measured at sense . a compen - sation capacitor at gate stabilizes this loop. a comparator monitors gate to ensure that it is low before allowing an initial timing cycle, gate ramp-up after an overvoltage event or restart after a current limit fault. during gate start-up, a second comparator detects if gate is within 2.8v of v in before pwrgd is set (ms package only). drain (pin 7/pin 6): drain sense input. connecting an external resistor, r d , between this pin and the mosfets drain (v out ) allows voltage sensing below 6.15v (5v for ltc4252c) and current feedback to timer. a comparator detects if drain is below 2.385v and together with the gate high comparator sets the pwrgd flag. if v out is above v drncl , drain clamps at approximately v drncl . the current through r d is internally multiplied by 8 and added to timers 230a pull-up current during a circuit breaker fault cycle. this reduces the fault time and mos- fet heating. ov ( pin 8/pin 7): overvoltage input. the active high thresh- old at the ov pin is set at 6.15v with 0.6v hysteresis. if ov > 6.15 v, gate pulls low. when ov returns below 5.55v, gate start-up begins without an initial timing cycle. the ltc4252c ov pin is set at 5.09v with 102mv hysteresis. if ov > 5.09v, gate pulls low. when ov returns below 4.988v, gate start-up begins without an initial timing cycle. if an overvoltage condition occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after the overvoltage condition goes away. an overvoltage condition does not reset the pwrgd flag . the internal uvlo at v in always overrides ov. a 1nf to 10nf capacitor at ov prevents transients and switching noise from affecting the ov thresholds and prevents glitches at the gate pin. uv ( pin 9/pin 7): undervoltage input . the active low thresh - old at the uv pin is set at 2.925v with 0.3v hysteresis. if uv < 2.925 v, pwrgd pulls high, both gate and timer pull low. if uv rises above 3.225v, this initiates an initial timing cycle followed by gate start-up. the ltc4252c uv pin is set at 3.08v with 324mv hysteresis. if uv < 2.756v, pwrgd pulls high, both gate and timer pull low. if uv rises above 3.08v, this initiates an initial timing cycle followed by gate start-up. the internal uvlo at v in always overrides uv. a low at uv resets an internal fault latch. a 1nf to 10nf capacitor at uv prevents transients and switching noise from affecting the uv thresholds and prevents glitches at the gate pin. timer (pin 10/pin 8): timer input. timer is used to generate an initial timing delay at start-up and to delay shutdown in the event of an output overload ( circuit breaker fault). timer starts an initial timing cycle when the following conditions are met: uv is high, ov is low, v in clears uvlo, timer pin is low, gate is lower than v gatel , ss < 0.2 v, and v sense C v ee < v cb . a pull-up current of 5.8a then charges c t , generating a time delay. if c t charges to v tmrh (4v ), the timing cycle terminates, timer quickly pulls low and gate is activated. if sense exceeds 50 mv while gate is high , a circuit breaker cycle begins with a 230a pull-up current charging c t . if drain is approximately 7v (6v for ltc4252c) during this cycle, the timer pull-up has an additional current of 8 ? i drn . if sense drops below 50mv before timer reaches 4v, a 5.8a pull-down current slowly discharges the c t . in the event that c t eventually integrates up to the v tmrh threshold, the circuit breaker trips, gate quickly pulls low and pwrgd pulls high. the ltc4252-1 timer pin latches high with a 5.8a pull-up source . this latched fault is cleared by either pulling timer low with an external device or by pulling uv below v uvlo . the ltc 4252 -2 starts a shutdown cooling cycle following an overcurrent fault. this cycle consists of 4 discharging ramps and 3 charging ramps. the charging and discharging currents are 5.8a and timer ramps between its 1v and 4v thresholds . at the completion of a shutdown cooling cycle, the ltc4252-2 attempts a start-up cycle.
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 11 4252b12f block diagram ? + 4252b12 bd ? ( + ) + ( ? ) ? + ? + ? + + ? + ? v in v in v ee v ee r ss v ee v ee v ee 0.5v v ee v ee v ee 5.8a 5.8a v in v ee v in 6.15v (5v) 58a 230a v in 22a (28a) 95k (47.5k) timer 6.15v (5.09v) 2.925v (3.08v) 4v 1v + ? + ? 2.385v v ee v ee v os = 10mv v in 2.8v ? + uv * gate sense v in v ee 58a pwrgd ** drain ov * ss v in cb 50mv + ? ? + fcl 200mv + ? acl 5k (2.5k) + ? 1 1 8 1 logic *ov and uv are tied together on the ms8 package. ov and uv are separate pins on the ms package ** only available in the ms package for components, current and voltage with two values, values in parentheses refer to the ltc4252c. values without parentheses refer to the ltc4252b
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 12 4252b12f operation hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. the flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. the ltc4252 is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. initial start-up the ltc4252 resides on a removable circuit board and controls the path between the connector and load or power conversion circuitry with an external mosfet switch (see figure 1). both inrush control and short- circuit protection are provided by the mosfet. a detailed schematic for the ltc 4252 c is shown in figure ?2 . C 48v and C48 rtn receive power through the longest con- nector pins and are the first to connect when the board is inserted. the gate pin holds the mosfet off during this time. uv and ov determine whether or not the mosfet should be turned on based upon internal high accuracy thresholds and an external divider. uv and ov do double duty by also monitoring whether or not the connector is seated. the top of the divider detects C48 rtn by way of a short connector pin that is the last to mate during the insertion sequence. interlock conditions a start-up sequence commences once these interlock conditions are met. 1. the input voltage v in exceeds v lko (uvlo). 2. the voltage at uv > v uvhi . 3. the voltage at ov < v ovlo . 4. the (sense C v ee ) voltage is < 50mv (v cb ). 5. the voltage at ss is < 0.2v (20 ? v os ). 6. the voltage on the timer capacitor ( c t ) is < 1 v (v tmrl ). 7. the voltage at gate is < 0.5v (v gatel ). the first three conditions are continuously monitored and the latter four are checked prior to initial timing or gate ramp-up. upon exiting an ov condition, the timer pin voltage requirement is inhibited. details are described in the applications information, timing waveforms section . timer begins the start-up sequence by sourcing 5.8 a into c t . if v in , uv or ov falls out of range, the start-up cycle stops and timer discharges c t to less than 1v, then waits until the aforementioned conditions are once again met. if c t successfully charges to 4v, timer pulls low and both ss and gate pins are released. gate sources 58a (i gate ), charging the mosfet gate and associated capacitance. the ss voltage ramp limits v sense to control the inrush current. pwrgd pulls active low when gate is within 2.8v of v in and drain is lower than v drnl . 4252b12 f01 ltc4252 c load isolated dc/dc converter module low voltage circuitry + + ? ? plug-in board backplane ?48rtn ?48v long long + figure 1. basic ltc4252 hot swap topology figure 2. C 48v, 2.5a hot swap controller 4252b12 f02 ?48rtn ?48v uv ov timer v ee v in sense gate ss drain ltc4252c-1 r1 392k 1% d in + ddz13b** r2 30.1k 1% r d 1m c t 0.68f c ss 68nf c c 10nf r s 0.02 q1 irf530s r c 10 r in 3 1.8k in series 1/4w each c1 10nf c in 1f c load 100f long long short + **diodes, inc ? recommended for harsh environments
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 13 4252b12f operation tw o modes of operation are possible during the time the mosfet is first turning on, depending on the values of external components, mosfet characteristics and nominal design current. one possibility is that the mosfet will turn on gradually so that the inrush into the load capacitance remains a low value. the output will simply ramp to C48v and the ltc4252 will fully enhance the mosfet. a second possibility is that the load current exceeds the soft-start current limit threshold of [v ss (t )/20 C v os ]/r s . in this case the ltc4252 will ramp the output by sourcing soft-start limited current into the load capacitance. if the soft-start voltage is below 1.2v, the circuit breaker timer is held low. above 1.2v, timer ramps up. it is important to set the timer delay so that, regardless of which start-up mode is used, the timer ramp is less than one circuit breaker delay time. if this condition is not met, the ltc4252 - 1 may shut down after one circuit breaker delay time whereas the ltc4252-2 may continue to autoretry. board removal if the board is withdrawn from the card cage, the uv and ov divider is the first to lose connection. this shuts off the mosfet and commutates the flow of current in the connector. when the power pins subsequently separate, there is no arcing. current control three levels of protection handle short- circuit and over - load conditions. load current is monitored by sense and resistor r s . there are three distinct thresholds at sense: 50mv for a timed circuit breaker function; 100mv for an analog current limit loop (60mv for the ltc4252c); and 200mv for a fast, feedforward comparator which limits peak current in the event of a catastrophic short- circuit. if, owing to an output overload, the voltage drop across r s exceeds 50mv, timer sources 230a into c t . c t even- tually charges to a 4v threshold and the ltc4252 shuts off. if the overload goes away before c t reaches 4v and sense measures less than 50mv, c t slowly discharges (5.8a). in this way the ltc4252s circuit breaker function responds to low duty cycle overloads and accounts for fast heating and slow cooling characteristics of the mosfet. higher overloads are handled by an analog current limit loop. if the drop across r s reaches v acl , the current limiting loop servos the mosfet gate and maintains a constant output current of v acl / r s . in current limit mode, v out typically rises and this increases mosfet heating. if v out > v drncl , connecting an external resistor, r d , between v out and drain allows the fault timing cycle to be shortened by accelerating the charging of the timer capacitor. the timer pull- up current is increased by 8 ? i drn . note that because sense > 50 mv, timer charges c t during this time and the ltc4252 will eventually shut down. low impedance failures on the load side of the ltc4252 coupled with 48v or more driving potential can produce current slew rates well in excess of 50a/s. under these conditions, overshoot is inevitable. a fast sense com- parator with a threshold of 200mv detects overshoot and pulls gate low much harder and hence much faster than the weaker current limit loop. the v acl /r s current limit loop then takes over and servos the current as previously described. as before, timer runs and shuts down the ltc4252 when c t reaches 4v. if c t reaches 4v, the ltc4252-1 latches off with a 5.8a pull-up current source whereas the ltc4252-2 starts a shutdown cooling cycle. the ltc4252-1 circuit breaker latch is reset by either pulling uv momentarily low or dropping the input voltage v in below the internal uvlo threshold or pulling timer momentarily low with a switch . the ltc4252-2 retries after its shutdown cooling cycle. although short- circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. noise spikes from the backplane or load, input steps caused by the connection of a second , higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the inser - tion of non-hot-swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. the action of timer and c t rejects these events allowing the ltc4252 to ride out temporary overloads and disturbances that could trip a simple current comparator and , in some cases , blow a fuse .
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 14 4252b12f shunt regulator a fast responding shunt regulator clamps the v in pin to 13v ( vz). power is derived from C48 rtn by an external current limiting resistor, r in . a 1f decoupling capacitor, c in filters supply transients and contributes a short delay at start- up. to meet creepage requirements r in may be split into two or more series connected units. this introduces a wider total spacing than is possible with a single component while at the same time ballasting the potential across the gap under each resistor. the ltc4252 is fundamentally a low voltage device that operates with C48v as its reference ground. to further protect against arc discharge into its pins, the area in and around the ltc4252 and all associated components should be free of any other planes such as chassis ground, return, or secondary - side power and ground planes. v in may be biased with additional current up to 30ma to accommodate external loading such as the pwrgd opto- coupler shown in figure 23. as an alternative to running higher current, simply buffer v in with an emitter follower as shown in figure 3. another method shown in figure 19 cascodes the pwrgd output. v in is rated handle 30ma within the thermal limits of the package , and is tested to survive a 100 s , 100 ma pulse . to protect v in against damage from higher amplitude spikes, clamp v in to v ee with a 13v zener diode. star connect v ee and all v ee -referred components to the sense resistor applications information kelvin terminal as illustrated in figure 3, keeping trace lengths between v in , c in , d in and v ee as short as possible. internal undervoltage lockout (uvlo) a hysteretic comparator, uvlo, monitors v in for undervolt - age. the thresholds are defined by v lko and its hysteresis, v lkh . when v in rises above v lko the chip is enabled ; below (v lko C v lkh ) it is disabled and gate is pulled low. the uvlo function at v in should not be confused with the uv/ov pin(s). these are completely separate functions. uv/ov comparators (ltc4252b) an uv hysteretic comparator detects undervoltage condi- tions at the uv pin, with the following thresholds: uv low-to-high (v uvhi ) = 3.225v uv high-to-low (v uvlo ) = 2.925v an ov hysteretic comparator detects overvoltage condi- tions at the ov pin, with the following thresholds: ov low-to-high (v ovhi ) = 6.150v ov high-to-low (v ovlo ) = 5.550v the uv and ov trip point ratio is designed to match the standard telecom operating range of 43v to 82v when con- nected together as in the typical application. a divider ( r 1, r 2) is used to scale the supply voltage. using r 1 = 402k 4252b12 f03 ?48rtn uv ov v ee v in sense ss timer gate pwrgd drain ltc4252b-1 r1 432k 1% r3 38.3k 1% r2 4.75k 1% c t 330nf c ss 68nf c c 18nf ?48v r s 0.02 q1 irf530s r c 10 r5 2.2k q2 r in 10k 1/2w 1 9 8 10 3 2 7 6 4 5 c2 10nf c in 1f c l 100f ?48rtn (short pin) + r d 1m load en r4 22k * * m0c207 q2: mmbt5551lt1 **diodes, inc ? recommended for harsh environments d in ? ddz13b ** figure 3. C 48v/2.5a application with different input operating range
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 15 4252b12f applications information and r 2 = 32.4k gives a typical operating range of 43.2v to 82.5v . the undervoltage shutdown and overvoltage recovery thresholds are then 39.2v and 74.4v . 1% divider resistors are recommended to preserve threshold accuracy . the r1-r2 divider values shown in the typical application set a standing current of slightly more than 100a and define an impedance at uv/ov of 30k. in most applica- tions , 30 k impedance coupled with 300 mv uv hysteresis makes the ltc4252b insensitive to noise. if more noise immunity is desired, add a 1nf to 10nf filter capacitor from uv/ov to v ee . separate uv and ov pins are available in the 10-pin ms package and can be used for a different operating range such as 35.5v to 76v as shown in figure 3. other combi- nations are possible with different resistor arrangements. uv/ov comparators (ltc4252c) a uv hysteretic comparator detects undervoltage condi- tions at the uv pin, with the following thresholds: uv low-to-high (v uv ) = 3.08v uv high-to-low (v uv C v uvhst ) = 2.756v an ov hysteretic comparator detects overvoltage condi- tions at the ov pin, with the following thresholds: ov low-to-high (v ov ) = 5.09v ov high-to-low (v ov C v ovhst ) = 4.988v the uv and ov trip point ratio is designed to match the standard telecom operating range of 43 v to 71 v when connected together as in figure 2. a divider ( r 1, r 2) is used to scale the supply voltage. using r 1 = 390 k and r 2 = 30.1k gives a typical operating range of 43v to 71v . the undervoltage shutdown and overvoltage recovery thresh - olds are then 38.5v and 69.6v respectively. 1% divider resistors are recommended to preserve threshold accuracy . the r 1-r 2 divider values shown in figure 2 set a standing current of slightly more than 100 a and define an impedance at uv/ ov of 28k . in most applications, 28k impedance coupled with 324mv uv hysteresis makes the ltc4252c insensitive to noise. if more noise immunity is desired, add a 1 nf to 10nf filter capacitor from uv/ ov to v ee . the uv and ov pins can be used for a wider operat- ing range such as 35.5v to 76v as shown in figure 4. other combinations are possible with different resistor arrangements. uv/ov operation a low input to the uv comparator will reset the chip and pull the gate and timer pins low. a low-to-high uv transition will initiate an initial timing sequence if the other interlock 4252b12 f04 ?48rtn uv ov v ee v in sense ss timer gate pwrgd drain ltc4252c-1 r1 464k 1% r3 34k 1% r2 10k 1% c t 0.68f c ss 68nf c c 10nf ?48v r s 0.02 q1 irf530s r c 10 r5 2.2k q2 r in 10k 1/2w 1 9 8 10 3 2 7 6 4 5 c2 10nf c in 1f c l 100f ?48rtn (short pin) + r d 1m load en r4 22k * * m0c207 q2: mmbt5551lt1 **diodes, inc ? recommended for harsh environments d in ? ddz13b ** figure 4. C 48v/2.5a application with wider input operating range
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 16 4252b12f applications information conditions are met. a high-to-low transition in the uv comparator immediately shuts down the ltc4252, pulls the mosfet gate low and resets the latched pwrgd high. overvoltage conditions detected by the ov comparator will also pull gate low, thereby shutting down the load. however, it will not reset the circuit breaker timer, pwrgd flag or shutdown cooling timer. returning the supply voltage to an acceptable range restarts the gate pin if all the interlock conditions except timer are met. only during the initial timing cycle does an ov condition reset the timer. drain connecting an external resistor, r d , to the dual function drain pin allows v out sensing* without it being dam- aged by large voltage transients. below 5v, negligible pin leakage allows a drain low comparator to detect v out less than 2.385v (v drnl ). this condition, together with the gate low comparator, sets the pwrgd flag. if v out > v drncl , the drain pin is clamped at about v drncl and the current flowing in r d is given by: i drn v out -v drncl r d (1) this current is scaled up 8 times during a circuit breaker fault and is added to the nominal 230a timer current. this accelerates the fault timer pull-up when the mos- fets drain- source voltage exceeds v drncl and effectively shortens the mosfet heating duration. timer the operation of the timer pin is somewhat complex as it handles several key functions. a capacitor c t is used at timer to provide timing for the ltc4252. four different charging and discharging modes are available at timer: 1) a 5.8a slow charge; initial timing and shutdown cool- ing delay. 2) a (230a + 8 ? i drn ) fast charge; circuit breaker delay. 3) a 5.8a slow discharge; circuit breaker cool off and shutdown cooling. 4) low impedance switch; resets the timer capacitor after an initial timing delay, in uvlo, in uv and in ov during initial timing. for initial start-up, the 5.8a pull-up is used. the low impedance switch is turned off and the 5.8a current source is enabled when the interlock conditions are met. c t charges to 4v in a time period given by: t= 4v ? c t 5.8a (2) when c t reaches 4v (v tmrh ), the low impedance switch turns on and discharges c t . a gate start-up cycle begins and both ss and gate are released. circuit breaker timer operation if the sense pin detects more than a 50mv drop across r s , the timer pin charges c t with (230a + 8 ? i drn ). if c t charges to 4v, the gate pin pulls low and the ltc 4252 - 1 latches off while the ltc4252-2 starts a shutdown cooling cycle. the ltc4252-1 remains latched off until the uv pin is momentarily pulsed low or timer is momentarily discharged low by an external switch or v in dips below uvlo and is then restored. the circuit breaker timeout period is given by: t= 4v ? c t 230a +8 ? i drn (3) if v out < 5v, an internal pmos device isolates any drain pin leakage current, making i drn = 0a in equation (3). if v out > v drncl during the circuit breaker fault period, the charging of c t accelerates by 8 ? i drn of equation (1). intermittent overloads may exceed the 50mv threshold at sense, but, if their duration is sufficiently short, timer will not reach 4v and the ltc4252 will not shut the external mosfet off . to handle this situation , the timer discharges c t slowly with a 5.8a pull-down whenever the sense voltage is less than 50mv. therefore, any intermittent overload with v out > 5v and an aggregate duty cycle of *v out as viewed by the mosfet; i.e., v ds .
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 17 4252b12f applications information 2.5% or more will eventually trip the circuit breaker and shut down the ltc 4252 . figure 5 shows the circuit breaker response time in seconds normalized to 1f for i drn = 0a. the asymmetric charging and discharging of c t is a fair gauge of mosfet heating. the normalized circuit response time is estimated by t c t (f) = 4 235.8+8 ? i drn ( ) ? dC5.8 ? ? ? ? (4) shutdown cooling cycle for the ltc4252-1 (latchoff version), timer latches high with a 5.8a pull-up after the circuit breaker fault timer reaches 4v. for the ltc4252 -2 (automatic retry ver - sion), a shutdown cooling cycle begins if timer reaches the 4v threshold. timer starts with a 5.8a pull-down until it reaches the 1v threshold. then, the 5.8a pull-up turns back on until timer reaches the 4v threshold. four 5.8a pull-down cycles and three 5.8a pull-up cycles occur between the 1v and 4v thresholds, creating a time interval given by: t shutdown = 7 ? 3v ? c t 5.8a (5) at the 1v threshold of the last pull-down cycle, a gate ramp-up is attempted. soft - start soft-start limits the inrush current profile during gate start-up. unduly long soft-start intervals can exceed the mosfets soa rating if powering up into an active load. if ss floats, an internal current source ramps ss from 0v to 2.2v for the ltc4252b or 0v to 1.4v for the ltc4252c in about 230s. connecting an external capacitor c ss from ss to ground modifies the ramp to approximate an rc response of: v ss (t)v ss ? 1Ce C t r ss ? c ss ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (6) an internal resistive divider (95k/5k for the ltc4252b or 47.5k/2.5k for the ltc4252c) scales v ss (t) down by 20 times to give the analog current limit threshold: v acl (t)= v ss (t) 20 Cv os (7) this allows the inrush current to be limited to v acl (t)/r s . the offset voltage, v os (10mv), ensures c ss is sufficiently discharged and the acl amplifier is in current limit before gate start-up. ss is pulled low under any of the following conditions: in uvlo, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. gate gate is pulled low to v ee under any of the following conditions: in uvlo, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. when gate turns on, a 58a current source charges the mosfet gate and any associated external capacitance. v in limits the gate drive to no more than 14.5v. gate- drain capacitance (c gd ) feedthrough at the first abrupt application of power can cause a gate- source voltage sufficient to turn on the mosfet. a unique circuit pulls gate low with practically no usable voltage at v in fault duty cycle (%) 0 20 40 60 80 100 normalized response time (s/f) 10 1 0.1 0.01 4252b12 f05 = 4 [(235.8 + 8 ? i drn ) ? d C 5.8] t c t (f) i drn = 0a figure 5. circuit-breaker response time
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 18 4252b12f applications information and eliminates current spikes at insertion. a large external gate- source capacitor is thus unnecessary for the purpose of compensating c gd . instead, a smaller value ( 10nf) capacitor c c is adequate. c c also provides compensation for the analog current limit loop. gate has two comparators: the gate low comparator looks for < 0.5 v threshold prior to initial timing or a gate start-up cycle; the gate high comparator looks for < 2.8v relative to v in and, together with the drain low compara- tor, sets pwrgd status during gate startup. sense the sense pin is monitored by the circuit breaker (cb) comparator, the analog current limit (acl) amplifier and the fast current limit (fcl) comparator. each of these three measures the potential of sense relative to v ee . when sense exceeds 50mv, the cb comparator activates the 230 a timer pull - up . at 100 mv (60 mv for the ltc 4252 c ), the acl amplifier servos the mosfet current and, at 200mv, the fcl comparator abruptly pulls gate low in an attempt to bring the mosfet current under control. if any of these conditions persists long enough for timer to charge c t to 4v (see equation ?3), the ltc4252 shuts down and pulls gate low. if the sense pin encounters a voltage greater than v acl , the acl amplifier will servo gate downwards in an attempt to control the mosfet current. since gate overdrives the mosfet in normal operation , the acl amplifier needs time to discharge gate to the threshold of the mosfet. for a mild overload the acl amplifier can control the mosfet current, but in the event of a severe overload the current may overshoot. at sense = 200mv the fcl comparator takes over, quickly discharging the gate pin to near v ee potential. fcl then releases and the acl amplifier takes over. all the while timer is running. the effect of fcl is to add a nonlinear response to the control loop in favor of reducing mosfet current. owing to inductive effects in the system, fcl typically over corrects the current limit loop and gate undershoots. a zero in the loop (resistor r c in series with the gate capaci- tor) helps the acl amplifier to recover. short -circuit operation circuit behavior arising from a load side low impedance short is shown in figure 6 for the ltc4252. initially, the current overshoots the fast current limit level of v sense = 200mv ( trace 2) as the gate pin works to bring v gs under control ( trace 3). the overshoot glitches the backplane in the negative direction and when the current is reduced to 100mv/r s , the backplane responds by glitching in the positive direction. timer commences charging c t ( trace 4) while the analog current limit loop maintains the fault current at 100mv/r s , which in this case is 5a ( trace 2). note that the backplane voltage ( trace 1) sags under load. timer pull-up is ac- celerated by v out . when c t reaches 4v, gate turns off, pwrgd pulls high, the load current drops to zero and the backplane rings up to over 100v. the transient associated with the gate turn off can be controlled with a snubber to reduce ringing and a transient voltage suppressor ( such as diodes inc. smat 70a) to clip off large spikes. the choice of rc for the snubber is usually done experimentally. the value of the snubber capacitor is usually chosen between 10 to 100 times the mosfet c oss . the value of the snub- ber resistor is typically between 3 to 100. 4252b12 f06 ?48rtn 50v/div gate 10v/div sense 200mv/div timer 5v/div 0.5ms/div fast current limit supply ring owing to current overshoot supply ring owing to mosfet turn off analog current limit onset of output short-circuit c timer ramp latch off figure 6. output short-circuit behavior of ltc4252
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 19 4252b12f applications information a low impedance short on one card may influence the behavior of others sharing the same backplane. the initial glitch and backplane sag as seen in figure 6 trace 1, can rob charge from output capacitors on adjacent cards. when the faulty card shuts down, current flows in to refresh the capacitors. if ltc4252s are used by the other cards, they respond by limiting the inrush current to a value of 100mv/r s . if c t is sized correctly, the capacitors will recharge long before c t times out. power good, pwrgd pwrgd latches low if gate charges up to within 2.8v of v in and drain pulls below v drnl during start -up . pwrgd is reset in uvlo, in a uv condition or if c t charges up to 4v. an overvoltage condition has no effect on pwrgd status. a 58a current pulls this pin high during reset. due to voltage transients between the power module and pwrgd , optoisolation is recommended . this pin provides sufficient drive for an opto-coupler. figure 19 shows an alternative npn configuration with a limiting base resistor for the pwrgd interface . the module enable input should have protection from the negative input current. mosfet selection the external mosfet switch must have adequate safe operating area (soa) to handle short- circuit conditions until timer times out. these considerations take prece- dence over dc current ratings. a mosfet with adequate soa for a given application can always handle the required current, but the opposite may not be true. consult the manufacturers mosfet data sheet for safe operating area and effective transient thermal impedance curves. mosfet selection is a 3-step process by assuming the absence of a soft - start capacitor . first , r s is calculated and then the time required to charge the load capacitance is determined . this timing , along with the maximum short- circuit current and maximum input voltage defines an operating point that is checked against the mosfets soa curve. to begin a design, first specify the required load current and ioad capacitance, i l and c l . the circuit breaker cur - rent trip point (v cb /r s ) should be set to accommodate the maximum load current. note that maximum input current to a dc/dc converter is expected at v supply (min) . r s is given by: r s = v cb(min) i l(max) (8) where v cb(min) = 40mv (45mv for ltc4252c) represents the guaranteed minimum circuit breaker threshold. during the initial charging process, the ltc4252b may operate the mosfet in current limit, forcing ( v acl ) between 80mv to 120mv (v acl is 54mv to 66mv for ltc4252c) across r s . the minimum inrush current is given by: i inrush(min) = 80mv r s (9) maximum short- circuit current limit is calculated using the maximum v acl . this gives i shortcircuit(max) = 120mv r s (10) the timer capacitor c t must be selected based on the slowest expected charging rate; otherwise timer might time out before the load capacitor is fully charged. a value for c t is calculated based on the maximum time it takes the load capacitor to charge. that time is given by: t cl(charge) = c ? v i = c l ? v supply(max) i inrush(min) (11) the maximum current flowing in the drain pin is given by: i drn(max) = v supply(max) Cv drncl r d (12)
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 20 4252b12f approximating a linear charging rate as i drn drops from i drn(max) to zero, the i drn component in equation (3) can be approximated with 0.5 ? i drn(max) . rearranging equation, timer capacitor c t is given by: c t = t cl(charge) ? 230a + 4 ? i drn(max) ( ) 4v (13) returning to equation (3), the timer period is calcu- lated and used in conjunction with v supply (max) and i shortcircuit (max) to check the soa curves of a prospec- tive mosfet. as a numerical design example, consider a 30w load, which requires 1a input current at 36v. if v supply (max) = 72v and c l = 100 f, r d = 1 m, equation (8) gives r s = 40m; equation (13) gives c t = 441nf. to account for errors in r s , c t , timer current (230a), timer threshold (4v), r d , drain current multiplier and drain voltage clamp (v drncl ), the calculated value should be multiplied by 1.5, giving the nearest standard value of c t = 680nf. if a short - circuit occurs , a current of up to 120 mv/40 m ?= ?3 a will flow in the mosfet for 5.6 ms as dictated by c t ?=?680 nf in equation (3). the mosfet must be selected based on this criterion. the irf530s can handle 100v and 3a for 10ms and is safe to use in this application. computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear mosfets soa characteristics and the r ss c ss response. an overly conservative but simple approach begins with the maximum circuit breaker current, given by: i cb(max) = v cb(max) r s (14) where v cb(max) = 60mv (55mv for the ltc4252c). from the soa curves of a prospective mosfet, determine the time allowed, t soa(max) . c ss is given by: c ss = t soa(max) 0.916 ? r ss (15) in the above example, 60mv/40m gives 1.5a. t soa(max) for the irf530s is 40ms. from equation (15), c ss = 437nf. actual board evaluation showed that c ss = 100 nf was appropriate. the ratio (r ss ? c ss ) to t cl(charge) is a good gauge as a large ratio may result in the time-out period expiring. this gauge is determined empirically with board level evaluation. summary of design flow to summarize the design flow, consider the application shown in figure 2 with the ltc4252c. it was designed for 80w. calculate the maximum load current : 80w/43v = 1.86 a; allowing for 83% converter efficiency, i in(max) = 2.2a. calculate r s : from equation (8) r s = 20m. calculate i shortcircuit (max) : from equation (10) i shortcircuit(max) = 66mv 20m? =3.3a select a mosfet that can handle 3.3a at 71v: irf530s. calculate c t : from equation (13) c t = 322nf. select c t ? =? 680 nf, which gives the circuit breaker time-out period t?= 5.6ms. consult mosfet soa curves : the irf530s can handle 3.3a at 100v for 8.2ms, so it is safe to use in this application. calculate c ss : using equations (14) and (15) select c ss ?=?68nf. frequency compensation the ltc 4252 c typical frequency compensation network for the analog current limit loop is a series r c (10) and c c connected to v ee . figure 7 depicts the relationship between the compensation capacitor c c and the mosfets c iss . the line in figure 7 is used to select a starting value for c c based upon the mosfets c iss specification. optimized values for c c are shown for several popular mosfets . differences in the optimized value of c c versus the starting value are small . nevertheless , compensation values should be verified by board level short- circuit testing. applications information
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 21 4252b12f applications information as seen in figure 6 previously, at the onset of a short- circuit event, the input supply voltage can ring dramatically owing to series inductance. if this voltage avalanches the mosfet, current continues to flow through the mosfet to the output. the analog current limit loop cannot control this current flow and therefore the loop undershoots. this effect cannot be eliminated by frequency compensation. a zener diode is required to clamp the input supply voltage and prevent mosfet avalanche. sense resistor considerations for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc 4252 s v ee and sense pins are strongly recommended. the drawing in figure 8 illustrates the correct way of making connections between the ltc4252 and the sense resis- tor. pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. timing waveforms system power-up figure 9 details the timing waveforms for a typical power- up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. at mosfet c iss (pf) 0 compensation capacitance c c (nf) 60 50 40 30 20 10 0 2000 4000 4252b12 f07 6000 8000 nty100n10 irf3710 irf540s irf530s irf740 figure 7. recommended compensation capacitor c c vs mosfet c iss figure 8. making pcb connections to the sense resistor w current flow from load current flow to ?48v backplane sense resistor track width w: 0.03" per amp on 1 oz copper to sense to v ee 4252b12 f08 time point 1, the supply ramps up, together with uv/ov, v out and drain. v in and pwrgd follow at a slower rate as set by the v in bypass capacitor. at time point 2, v in exceeds v lko and the internal logic checks for uv > v uvhi , ov < v ovlo , gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl . if all conditions are met, an initial timing cycle starts and the timer capacitor is charged by a 5.8a current source pull-up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capacitor is quickly discharged. at time point 4, the v tmrl threshold is reached and the condi- tions of gate < v gatel , sense < v cb and ss ? ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 22 4252b12f applications information at time point 8, the load current falls and the sense voltage drops below v acl ( t ). the analog current limit loop shuts off and the gate pin ramps further. at time point 9, the sense voltage drops below v cb , the fault timer cycle ends, followed by a 5.8a discharge cycle ( cool off). the duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid a fault time out during gate ramp- up. when gate ramps past the v gateh thresh- old at time point 10, pwrgd pulls low. at time point ?11, gate reaches its maximum voltage as determined by v in . live insertion with short pin control of uv/ov in the example shown in figure 10, power is delivered through long connector pins whereas the uv/ov divider makes contact through a short pin. this ensures the power connections are firmly established before the ltc4252 is activated. at time point 1, the power pins make contact and v in ramps through v lko . at time point 2, the uv/ov divider makes contact and its voltage exceeds v uvhi . in addition, the internal logic checks for ov < v ovhi , gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl . if all conditions are met, an initial timing cycle starts and the timer capacitor is charged by a 5.8a current source pull-up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capacitor is quickly discharged. at time point 4, the v tmrl threshold is reached and the conditions of gate < v gatel , sense < v cb and ss < 20 ? v os must be gnd ? v ee or (?48rtn) ? (?48v) uv/ov v in timer gate v lko sense v in clears v lko , check uv > v uvhi , ov < v ovlo , gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl v out 1 2 3 4 56 7 8 v acl v cb 9 timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ? v os ss drain pwrgd 230a + 8 ? i drn 5.8a 20 ? v os 58a 10 11 v in ? v gateh v drnl v drncl 20 ? (v cb + v os ) 20 ? (v acl + v os ) v gatel v tmrl v tmrh 5.8a 5.8a 58a 4252b12 f09 gate start-up initial timing figure 9. system power-up timing (all waveforms are referenced to v ee )
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 23 4252b12f applications information satisfied before a gate start-up cycle begins. ss ramps up as dictated by r ss ??? c ss ; gate is held low by the analog current limit amplifier until ss crosses 20 ? v os . upon releasing gate , 58a sources into the external mosfet gate and compensation network. when the gate voltage reaches the mosfets threshold, current begins flowing into the load capacitor at time point 5. at time point 6, load current reaches the ss control level and the analog current limit loop activates. between time points 6 and 8, the gate voltage is servoed , the sense voltage is regulated at v acl (t) and soft-start limits the slew rate of the load current. if the sense voltage (v sense C v ee ) reaches the v cb threshold at time point 7, the circuit breaker timer activates. the timer capacitor, c t , is charged by a (230a + 8 ? i drn ) current pull-up. as the load capacitor nears full charge, load current begins to decline. at point 8, the load current falls and the sense voltage drops below v acl (t). the analog current limit loop shuts off and the gate pin ramps further. at time point 9, the sense voltage drops below v cb and the fault timer cycle ends, followed by a 5.8a discharge cycle (cool off). when gate ramps past v gateh threshold at time point 10, pwrgd pulls low. at time point 11, gate reaches its maximum voltage as determined by v in . 5.8a 58a 5.8a 5.8a 58a gate start-up initial timing uv clears v uvhi , check ov < v ovhi , gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl 1 2 3 4 56 7 8 9 timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ? v os 1011 4252b12 f10 gnd ? v ee or (?48rtn) ? (?48v) uv/ov v in timer gate sense v out ss drain pwrgd v lko v uvhi v acl v cb 230a + 8 ? i drn 20 ? v os v in ? v gateh v drnl v drncl 20 ? (v cb + v os ) 20 ? (v acl + v os ) v gatel v tmrl v tmrh figure 10. power-up timing with a short pin (all waveforms are referenced to v ee )
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 24 4252b12f applications information undervoltage timing in figure 11 when uv pin drops below v uvlo ( time point ?1), the ltc4252 shuts down with timer, ss and gate all pulling low. if current has been flowing, the sense pin voltage decreases to zero as gate collapses. when uv recovers and clears v uvhi (time point 2), an initial timer cycle begins followed by a gate start-up cycle. v in undervoltage lockout timing the v in undervoltage lockout comparator, uvlo, has a similar timing behavior as the uv pin timing except it looks for v in < ( v lko C v lkh ) to shut down and v in > v lko to start. in an undervoltage lockout condition, both uv and ov comparators are held off. when v in exits undervoltage lockout, the uv and ov comparators are enabled. undervoltage timing with overvoltage glitch in figure 12, both uv and ov pins are connected together. when uv clears v uvhi (time point 1), an initial timing cycle starts. if the system bus voltage overshoots v ovhi as shown at time point 2, timer discharges. at time point 3, the supply voltage recovers and drops below the v ovlo threshold. the initial timing cycle restarts, followed by a gate start-up cycle. overvoltage timing during normal operation, if the ov pin exceeds v ovhi as shown at time point 1 of figure 13, the timer and pwrgd status are unaffected . nevertheless , ss and gate pull down and the load is disconnected. at time point 2, ov recovers and drops below the v ovlo threshold. a gate start-up cycle begins. if the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle as shown between time points 4 through 7 may occur. circuit breaker timing in figure 14a, the timer capacitor charges at 230a if the sense pin exceeds v cb but v drn is less than 5v. if the sense pin drops below v cb before timer reaches uv timer gate sense ss drain pwrgd 5.8a 58a 5.8a 5.8a 58a uv drops below v uvlo . gate, ss and timer are pulled down, pwrgd releases 1 2 3 4 56 7 8 9 timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ? v os 10 11 4252b12 f11 uv clears v uvhi , check ov condition, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl v acl v cb 230a + 8 ? i drn 20 ? v os v in ? v gateh v drnl v drncl 20 ? (v cb + v os ) 20 ? (v acl + v os ) v gatel v tmrl v tmrh v uvhi v uvlo gate start-up initial timing figure 11. undervoltage timing (all waveforms are referenced to v ee )
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 25 4252b12f applications information uv/ov timer gate sense ss drain pwrgd 5.8a 58a 58a 5.8a 5.8a uv/ov clears v uvhi , check ov condition, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl 1 2 3 4 5 67 8 9 timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ? v os 10 11 12 4252b12 f12 uv/ov drops below v ovlo and timer restarts initial timing cycle uv/ov overshoots v ovhi and timer aborts initial timing cycle v acl v cb 230a + 8 ? i drn 20 ? v os v in ? v gateh v drnl v drncl 20 ? (v cb + v os ) 20 ? (v acl + v os ) v gatel v tmrl v tmrh v ovhi v uvhi v ovlo gate start-up initial timing ov timer gate sense ss 5.8a 58a 58a 5.8a 1 2 34 5 67 8 9 4252b12 f13 ov drops below v ovlo , check gate < v gatel , sense < v cb and ss < 20 ? v os ov overshoots v ovhi . gate and ss are pulled down, pwrgd and timer are unaffected v acl v cb 230a + 8 ? i drn 20 ? v os v in ? v gateh 20 ? (v cb + v os ) 20 ? (v acl + v os ) v gatel v ovhi v tmrh v ovlo gate start-up figure 13. overvoltage timing (all waveforms are referenced to v ee ) figure 12. undervoltage timing with an overvoltage glitch (all waveforms are referenced to v ee )
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 26 4252b12f applications information cb fault timer gate sense v out ss drain pwrgd timer gate sense v out ss drain pwrgd timer gate sense v out ss drain pwrgd cb fault cb fault cb fault 5.8a 5.8a 1 2 4252b12 f14 1 2 cb times out 1 432 cb times out v acl v cb v acl v drncl v cb v acl v tmrh v tmrh v tmrh v cb 230a + 8 ? i drn v drncl 230a + 8 ? i drn 230a + 8 ? i drn 230a + 8 ? i drn (14a) momentary circuit-breaker fault figure 14. circuit-breaker timing behavior (all waveforms are referenced to v ee ) (14b) circuit-breaker time out (14c) multiple circuit-breaker fault the v tmrh threshold, timer is discharged by 5.8a. in figure 14b, when timer exceeds v tmrh , gate pulls down immediately and the ltc4252 shuts down. in figure 14c, multiple momentary faults cause the timer capacitor to integrate and reach v tmrh . gate pull down follows and the ltc4252 shuts down. during shutdown, the ltc4252 - 1 latches timer high with a 5.8a pull-up current source ; the ltc4252-2 activates a shutdown cooling cycle. resetting a fault latch (ltc4252-1) the latched circuit breaker fault of ltc4252-1 benefits from long cooling time. it is reset by pulling the uv pin below v uvlo with a switch. reset is also accomplished by pulling the v in pin momentarily below (v lko C v lkh ). a third reset method involves pulling the timer pin below v tmrl as shown in figure 15. an initial timing cycle is skipped if timer is used for reset. an initial timing cycle is generated if reset by the uv pin or the v in pin. the duration of the timer reset pulse should be smaller than the time taken to reach 0.2v at ss pin. with a single pole mechanical pushbutton switch , this may not be feasible. a double pole, single throw pushbutton switch removes this restriction by connecting the second switch to the ss pin. with this method, both the ss and timer pins are released at the same time (see figure 24). shutdown cooling cycle (ltc4252-2) figure 16 shows the timer behavior of the ltc4252-2. at time point 2, timer exceeds v tmrh , gate pulls down immediately and the ltc4252 shuts down. timer starts a shutdown cooling cycle by discharging timer with 5.8a to the v tmrl threshold. timer then charges with 5.8a to the v tmrh threshold. there are four 5.8a discharge phases and three 5.8a charge phases in this shutdown cooling cycle spanning time points 2 and 3. at time point 3, the ltc4252 automatic retry occurs with a start-up cycle. good thermal management techniques are highly recommended ; power and thermal dissipation must be carefully evaluated when implementing the automatic retry scheme.
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 27 4252b12f applications information timer gate sense v acl v cb ss drain 230a + 8 ? i drn v in ? v gateh v drnl 425212b f15 v drncl v gatel v tmrl v tmrh pwrgd 5.8a 5.8a 5.8a 58a 58a 1 2 34 5 67 8 9 switch releases ss switch resets latched timer gate start-up 20 ? v os 20 ? (v cb + v os ) 20 ? (v acl + v os ) momentary dpst switch reset timer gate sense v out v acl v cb ss drain 230a + 8 ? i drn v tmrh v tmrl v gatel 230a + 8 ? i drn v in ? v gateh v drnl 4252b12 f16 v drncl pwrgd 58a 58a 5.8a 5.8a 5.8a 5.8a 5.8a 5.8a 5.8a 5.8a 5.8a gate start-up shutdown cooling cb fault 20 ? v os 20 ? (v cb + v os ) 20 ? (v acl + v os ) 1 2 3 4 5 6 78 9 10 retry circuit breaker times out figure 16. shutdown cooling timing behavior of ltc4252-2 (all waveforms are referenced to v ee ) figure 15. pushbutton reset of ltc4252-1s latched fault (all waveforms are referenced to v ee )
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 28 4252b12f applications information analog current limit and fast current limit in figure 17a , when sense exceeds v acl , gate is regulated by the analog current limit amplifier loop. when sense drops below v acl , gate is allowed to pull up. in figure 17b, when a severe fault occurs, sense exceeds v fcl and gate immediately pulls down until the analog current amplifier establishes control. if the severe fault causes v out to exceed v drncl , the drain pin is clamped at v drncl . i drn flows into the drain pin and is multiplied by 8. this extra current is added to the timer pull-up current of 230a. this accelerated timer current of [230a +8 ? i drn ] produces a shorter circuit breaker fault delay. careful selection of c t , r d and mosfet can help prevent soa damage in a low impedance fault condition. soft-start if the ss pin is not connected, this pin defaults to a linear voltage ramp, from 0v to 2.2v in about 180s (or 0v to 1.4v in 230s for the ltc4252c) at gate start-up, as shown in figure 18a. if a soft-start capacitor, c ss , is con- nected to this ss pin, the soft-start response is modified from a linear ramp to an rc response (equation ?6), as shown in figure 18b. this feature allows load current to slowly ramp-up at gate start-up. soft-start is initiated at time point 3 by a timer transition from v tmrh to v tmrl (time points 1 to 2) or by the ov pin falling below the v ovlo threshold after an ov condition. when the ss pin is below 0.2v, the analog current limit amplifier holds gate low. above 0.2v, gate is released and 58a ramps up the compensation network and gate capacitance at time point 4. meanwhile, the ss pin voltage continues to ramp up. when gate reaches the mosfets threshold, the mosfet begins to conduct. due to the mosfets high g m , the mosfet current quickly reaches the soft-start control value of v acl (t) (equation 7). at time point 6, the gate voltage is controlled by the current limit amplifier. the soft-start control voltage reaches the circuit breaker voltage, v cb , at time point 7 and the circuit breaker timer activates. as the load capacitor nears full charge, load timer gate sense v out v acl v cb ss drain v tmrh 230a + 8 ? i drn 4252b12 f17 pwrgd 5.8a 5.8a timer gate sense v out v acl v cb v fcl ss drain v tmrh v drncl 230a + 8 ? i drn pwrgd 1 2 1 432 cb times out figure 17. current limit behavior (all waveforms are referenced to v ee ) (17a) analog current limit fault (17b) fast current limit fault
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 29 4252b12f applications information current begins to decline below v acl (t). the current limit loop shuts off and gate releases at time point 8. at time point ?9, the sense voltage falls below v cb and timer deactivates. large values of c ss can cause premature circuit breaker time out as v acl (t) may exceed the v cb potential during the circuit breaker delay. the load capacitor is unable to achieve full charge in one gate start-up cycle. a more serious side effect of large c ss values is soa duration may be exceeded during soft-start into a low impedance load. a soft-start voltage below v cb will not activate the circuit breaker timer. power limit circuit breaker figure 19 shows the ltc4252c-1 in a power limit circuit breaking application. the sense pin is modulated by the board supply voltage, v supply . the d1 zener voltage, v z is set to be the same as the low supply operating volt- age, v supply (min) = 43 v. if the goal is to have the high supply operating voltage, v supply (max) = 71v giving the same power at v supply (min) , then resistors r4 and r6 are selected using the ratio: r6 r4 = v cb v supply(max) (16) if r6 is 27, r4 is 38.3k. the peak circuit breaker power limit is: power max = v supply(min) +v supply(max) ( ) 2 4 ? v supply(min) ? v supply(max) ? power supply(min) =1.064 ? power supply(min) (17) when v supply = 0.5 ? (v supply (min) + v supply (max) ) = 57v. the peak power at the fault current limit occurs at the supply overvoltage threshold. the fault current limited power is: power fault = v supply r s ? v acl C v supply Cv z ( ) ? r6 r4 ? ? ? ? ? ? ( 18) timer gate sense ss drain v tmrh v drncl v acl v cb v drnl v gs(th) v in ? v gateh v tmrl 4252b12 f18 pwrgd 5.8a 58a 58a timer gate sense ss drain v tmrh v drncl v cb v acl v drnl v gs(th) v in ? v gateh v tmrl pwrgd 5.8a 58a 58a 12 34 567 7a 8 9 10 11 end of intial timing cycle 12 3 4 5 6 7 8 9 10 11 end of intial timing cycle 20 ? v os 20 ? (v cb + v os ) 20 ? (v acl + v os ) 20 ? v os 20 ? (v cb + v os ) 20 ? (v acl + v os ) 230a + 8 ? i drn 230a + 8 ? i drn figure 18. soft-start timing (all waveforms are referenced to v ee ) (18a) without external c ss (18b) with external c ss
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 30 4252b12f applications information 4252b12 f19 ?48rtn uv ov v ee v in sense ss timer gate pwrgd drain ltc4252c-1 r1 392k 1% r2 30.1k 1% c t 0.68f c ss 68nf c c 10nf ?48v r s 0.02 q1 irf530s v out r c 10 r5 100k r4 38.3k d1 bzv85c43 r in 3 1.8k 1/4w each 1 9 8 10 3 2 7 6 4 5 c1 10nf c in 1f c l 100f ?48rtn (short pin) + r d 1m r6 27 load en * *fmmt493 **diodes, inc ? recommended for harsh environments d in ? ddz13b ** figure 19. power limit circuit breaking application circuit breaker with foldback current limit figure 20 shows the ltc4252c in a foldback current limit application. when v out is shorted to the C 48v rtn supply, current flows through resistors r4 and r5. this results in a voltage drop across r5 and a corresponding reduction in voltage drop across the sense resistor, r s , as the acl amplifier servos the sense voltage between the sense and v ee pins to about 60mv. the short- circuit current through r s reduces as the v out voltage increases during an output short- circuit condition. without foldback current limiting resistor r5, the current is limited to 3a during analog current limit. with r5, the short- circuit current is limited to 0.5a when v out is shorted to 71v. inrush control without a sense resistor during power-up figure 21 shows the ltc4252c in an application where the inrush current is controlled without a sense resistor during power-up. this setup is suitable only for applications that dont require short- circuit protection from the ltc4252c. resistor r4 and capacitor c2 act as a feedback network to accurately control the inrush current. the c2 capacitor can be calculated with the following equation: c2= i gate ? c l i inrush (19) where i gate = 58a and c l is the total load capacitance. capacitor c3 and resistor r4 prevent q1 from momen- tarily turning on when the power pins first make contact. without c3 and r4, capacitor c2 pulls the gate of q1 up to a voltage roughly equal to v ee ? c2/c gs(q1) before the ltc4252c powers up. by placing capacitor c3 in parallel with the gate capacitance of q1 and isolating them from c2 using resistor r4, the problem is solved. the value of c3 is given by: c3= v supply(max) v gs(th),q1 ? c2+c gd(q1) ( ) (20) c3 35 ? c2 for v supply (max) = 71v where v gs( th),q 1 is the mosfet s minimum gate threshold and v supply (max) is the maximum operating input voltage. diode-oring figure 22 shows the ltc4252b used as diode-oring with hot swap capability in a dual C 48v power supply applica- tion. the conventional diode-or method uses two high power diodes and heat sinks to contain the large heat dissipation of the diodes. with the ltc4252b controlling the external fets q2 and q3 in a diode-or manner, the small turn-on voltage across the fully enhanced q2 and q3 reduces the power dissipation significantly.
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 31 4252b12f applications information 4252b12 f20 uv ov v ee v in sense ss timer gate pwrgd drain ltc4252c-1 r1 392k 1% r2 30.1k 1% c t 0.68f c ss 68nf c c 10nf ?48v r s 0.02 r4 38.3k q1 irf530s v out r c 10 r3 5.1k r in 3 1.8k 1/4w each 1 9 8 10 3 2 7 6 4 5 c1 10nf c in 1f c l 100f ?48rtn (short pin) ?48rtn r d 1m r5 27 r g 10 load en * *moc207 + **diodes, inc ? recommended for harsh environments d in ? ddz13b ** 4252b12 f21 uv ov v ee v in sense ss timer gate pwrgd drain ltc4252c-1 r1 392k 1% r2 30.1k 1% c t 0.68f c ss 68nf c3 330nf 25v c2 10nf 100v ?48v r4 1k 1% q1 irf530s v out r3 5.1k r in 3 1.8k 1/4w each 1 9 8 10 3 2 7 6 4 5 c1 10nf c in 1f c l 100f ?48rtn (short pin) ?48rtn r d 1m r g 10 load en * *moc207 **diodes, inc ? recommended for harsh environments d in ? ddz13b ** + figure 20. circuit breaker with foldback current limit application figure 21. inrush control without a sense resistor application at power-up, q5 and q8 are held off low by the ss pin of the ltc4252b; resistors r5 and r8 pull the sense pin closed to v ee . v ee is connected to the power supply with lower voltage through the body diodes q2 or q3 until q2 or q3 is turned on. this allows the ltc4252b to perform a start-up cycle and ramp up the ss and gate voltage. as the ss voltage ramps up to 2.2v , it turns on q 5 and q 8 and pulls timer low through q 6 and q 9. the sense voltage rises as current flows into r 5 and r 8 through resistors r 3 and r 6. the acl amplifier of the ltc4252b servos the sense voltage to about 100mv as the gate voltage regulates q 2 and q 3. current flows into r 4, q 4 and r 7, q 7 as q 2 and q 3 turn on. the respective node voltages at the r 3 and r 4 connection and the r 6 and r 7 connection are always kept equal to their respective sense voltages by the q 4 and q 2 v ds drop and the q 7 and q 3 v ds drop assuming the q 5 and q 8 v ds drop is negligible.
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 32 4252b12f applications information uv/ov v ee v in sense ss timer gate drain ltc4252b-1 r1 402k r2 32.4k c t 0.33f c ss 68nf c c1 22nf r c1 10 q1 irf530s rs 0.02 r in1 3 1.8k in series 1/4w each 1 7 8 2 6 5 3 4 c1 10nf c in 1f hot swap section diode-or circuit for channel a ?48rtn ?48v a r d 1m load module uv v ee v in sense ov r5 560 ss timer pwrgd gate drain ltc4252b-2 1 9 2 10 q6 fdv301n q5 fdv301n q2 irf530s q4 bss131 c in2 1f r in2 3 1.8k in series 1/4w each 3 8 7 4 6 5 r c2 10 r3 12k r4 150 c c2 22nf diode-or circuit for channel b ?48v b uv v ee v in sense ov r8 560 ss timer pwrgd gate drain ltc4252b-2 1 9 2 10 q9 fdv301n q8 fdv301n q3 irf530s q7 bss131 c in3 1f r in3 3 1.8k in series 1/4w each 3 8 7 4 6 5 r c3 10 r6 12k r7 150 c c3 22nf 4252b12 f22 d in1 ? ddz13b ** d in3 ? ddz13b ** d in2 ? ddz13b ** **diodes, inc ? recommended for harsh environments figure 22. C 48v/2.5a diode-or application
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 33 4252b12f applications information the internal fault latches of the ltc4252b are disabled as the timer pin is always held low by the ss voltage when q2 and q3 are in analog current limit. if both power supplies from channel a and b are exactly equal, then equal load current will flow through q2 and q3 to the load module via the hot swap section. if the channel a supply is greater than the channel b by more than 100mv, the sense voltage will rise above the fast comparator trip threshold of 200mv, the gate will be pulled low and q2 is turned off. the gate ramps up and regulates q2 when the channel a supply is equal to the channel b supply. likewise, if the channel b supply is greater than channel a by more than 100mv, it trips the fast comparator and gate is pulled low and q3 is turned off. the gate ramps up and regulates q 3 when the channel b supply is equal to the channel a supply. resistors r4, r7 and external fets q4 and q7 limit the current flow into q5 and q8 during their respective sup- ply source short. when the channel a supply is shorted to the C 48v rtn ( or gnd), large current flows into q4 momentarily and creates a voltage drop across r4, which in turn reduces the gate-to- source voltage of q4, limiting the current flow. the sense voltage is lifted up and causes the fast comparator of ltc4252b to trip and pull the gate low instantly. the channel a supply short will not cause q3 of channel b diode-or circuit to turn off. similarly, when the channel b supply is shorted to the C48v rtn (or gnd), large current flows into q7 momen- tarily and creates a voltage drop across r7, which in turn reduces the gate-to- source voltage of q7, thus limiting the current flow. the increase in sense voltage will trip the fast comparator of ltc4252b and pull the gate low instantly. the channel b supply short will not cause q2 of channel a diode-or circuit to turn off. the load short at the output of q1 is protected by the hot swap section. using an emi filter module many applications place an emi filter module in the power path to prevent switching noise of the module from being injected back onto the power supply. a typical application using the lucent fltr 100v10 filter module is shown in figure 23. when using a filter, an opto-isolator is required to prevent common mode transients from destroying the pwrgd and on/off pins. figure 23. typical application using a filter module 4252b12 f23 uv ov v ee v in sense ss timer gate pwrgd drain ltc4252c-1 r1 392k 1% r2 30.1k 1% c t 0.68f c ss 68nf c c 10nf ?48v r s 0.02 q1 irf530s 1n4003 v in + c2 0.1f 100v v in ? v out + v out ? r c 10 r3 5.1k r in 3 1.8k 1/4w 1 9 8 10 3 2 7 6 4 5 c1 10nf c in 1f ?48rtn (short pin) ?48rtn (long pin) r d 1m *moc207 * + c3 0.1f 100v c4 100f 100v c6 100f 16v c5 0.1f 100v lucent fltr100v10 case v in + on/off v in ? v out + 1 2 4 5 6 7 8 9 5v 3 sense + sense ? trim v out ? lucent jw050a1-e case + d in ? ddz13b ** **diodes, inc ? recommended for harsh environments
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 34 4252b12f package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 35 4252b12f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev e) msop (ms) 0307 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc 4252b-1/ ltc 4252b-2 ltc 4252c-1/ ltc 4252c-2 36 4252b12f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0112 ? printed in usa related parts typical application part number description comments LT1640AH/lt1640al negative high voltage hot swap controllers in so-8 negative high voltage supplies from C 10v to C 80v lt1641-1/lt1641-2 positive high voltage hot swap controllers in so-8 supplies from 9v to 80v, latched off/ autoretry ltc1642 fault protected hot swap controller 3v to 16.5v, overvoltage protection up to 33v ltc4214 negative voltage hot swap controller operates from C6v to C16v ltc4220 dual supply hot swap controller 2.2v to 16.5v operation lt4250 C 48v hot swap controller in so-8 active current limiting, supplies from C20v to C80v ltc4251b/ ltc4251b-1/ ltc4251b-2 C48v hot swap controllers in sot-23 fast active current limiting, supplies from C 15v ltc4253b C48v hot swap controller with sequencer fast current limiting with three sequenced power good outputs, supplies from C15v 4252b12 f24 ?48rtn uv/ov v ee v in sense ss timer gate drain ltc4252b-1 r1 402k 1% r2 32.4k 1% c t 150nf push reset c ss 27nf c c 22nf ?48v r s 0.01 q1 irf540s v out r c 10 r in 2 5.1k in series 1/4w each 1 7 8 2 6 5 3 4 c1 10nf c in 1f c l 100f ?48rtn (short pin) + r d 1m r3 22 load **diodes, inc ? recommended for harsh environments d in ? ddz13b ** figure 24. C 48v/5a application

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